1. Field of the Invention
The present invention generally relates to the design of integrated circuits and, more specifically, to testing and repairing of memory arrays in integrated circuits.
2. Description of Related Art
Memory components such as random access memories (RAM) are widely available in very high densities. It would be extremely cost inefficient to discard an entire integrated circuit chip simply because of the failure of a single memory cell in a memory. Accordingly, It is known to include circuitry which can both detect failures in a memory and also repair a defective memory. To facilitate providing repairable memory arrays, it is also known to divide such memories into segments. Each segment may be organized as a set of columns. Various methods have been devised for repairing memory arrays. The drawbacks of existing methods are that they require large chip area and repair reduces repair speed from that which would otherwise be desirable.
Kwon et al. in a paper entitled “Linear Search Algorithm for Repair Analysis with 4 Spare Row/4 Spare Column”, published as paper 15.1 in the proceedings of the IEEE Asia-Pacific Conference on ASIC, Cheju Island, Korea, Aug. 28th, 2000, discloses a method of repair analysis for repairing a RAM block, using four spare rows and four spare columns, implemented with CAM (Content Addressable Memory) that has the functions of data-match, count-sub-entry, search-empty-entry. The primary feature of the method is on-the-fly repair analysis by re-arrangement of CAM array contents and repair analysis processing by one row or one column unit with a dual error buffer.
A Schöber et al. paper entitled “Memory Built-In Self-Repair” describes a word oriented memory test methodology for Built-In Self-Repair (BISR) published in the 2001 Proceedings of the International Test Conference, October, 2001, p. 995. The method contains memory BIST logic, wrapper logic to replace defective words, and fuse boxes to store failing addresses to allow the use of RAMs without spare rows and spare columns used in classic redundancy concepts. Faulty addresses and expected data are stored in redundancy logic immediately after detection. The BISR adds faulty words to the redundancy logic as long as spare words are available to avoid external or internal redundancy calculation. It is possible to add faulty addresses to faults that have been detected during former runs. The memory test allows a memory BISR even if parts of the redundancy are already configured. The fuse box can be connected to a scan register to stream in and out data during test and redundancy configuration.
A Nakahara et al. paper, entitled “Built-in Self-test For GHz Embedded SRAMs Using Flexible Pattern Generator And New Repair Algorithm”, published in the 1999 Proceedings of the International Test Conference (ITC), Sep. 28, 1999, p. 301, discloses a built-in self-test (BIST) scheme which consists of a flexible pattern generator and an on-macro two-dimensional redundancy analyzer, for GHz embedded SRAMs. In order to meet system requirements and to detect a wide variety of faults or performance degradation resulting from recent technology advances, a microcode-based pattern generator is used to generate flexible patterns.
Bhavsar et al. U.S. Pat. No. 6,408,401 granted on Jun. 18, 2002 for “Embedded Ram with Self-test and Self-repair with Spare Rows and Columns” discloses a self-repair method for a random access memory (RAM) array which comprises testing a memory array to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compared to at least one address of at least one previously-discovered faulty memory cell. The address of the newly discovered faulty memory cell is stored if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell. Flags are set to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, if the row or column address of the newly-discovered memory cell matches the respective row or column address of the previously-discovered faulty memory cell. Spare rows and columns that have been indicated by the flags as requiring replacement are allocated to replace faulty rows and columns respectively. The remaining spare rows and columns whose row and column addresses respectively have been stored are then allocated. The RAM is flagged as un-repairable if an insufficient number of spare rows or spare cells remain to replace all of the rows or columns containing faulty cells.
Priore et al. U.S. Pat. No. 6,076,176 granted on Jun. 13, 2000 for “Encoding of Failing Bit Addresses to Facilitate Multi-bit Failure Detect Using a Wired-or Scheme” discloses a technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.